1. Technical Field
Generally, the present disclosure relates to integrated circuits, and, more particularly, to improvements in scan and built-in self-testing of integrated circuits.
2. Description of the Related Art
Semiconductor processors comprise many sequential elements, such as various flip flops and combinational logic, which form various complex circuits. During manufacturing and testing of semiconductor processors, various tests are applied. Often, the various circuit portions, such as sequential elements within a processor, must be tested to ensure proper operation of the processor. In many cases, data may be shifted into various sequential elements of the processor and resultant output may be scanned and verified for functional integrity. One of the problems associated with testing of various sequential elements of the processor includes the burden placed on the power supply upon a global shift of data into various sequential elements of the processor. For example, if a global scan signal is applied and de-asserted and an appreciable amount of time takes place between the de-assertion of the global signal and a master clock signal, the chip capacitance may have sufficiently discharged so that when starting up, an instance of power draw may cause an excessive draw of current, a so-called “di/dt” event (an excessive draw of current in a small amount of time). In this case, the excessive current demand may cause a drop in voltage, thereby causing potential operational errors of the various elements in the processor. Even if operational errors are avoided, the drop in voltage may lead to an erroneous underestimation of the maximum voltage and the maximum frequency at which the processor may be operable, thereby making it more difficult in categorizing products based upon performance.